IEEE Computer Society System Competition

http://www.computer.org/portal/web/competition/home

 

ISA

NFDL(network flow description language)

Flow

1. data ()
2. control
3. instructions
4. state (FSMs)

node, link, layer

nodes

1. 32 regs
2. r(i) or r(i:j) or ra(rb) to access bit/bits
3. reg vectors
   1. [r1,r2,r3].(0:1)
   2. vector also support sub accessing

Link

1. single transaction as a function of input nodes and output nodes
2. [r1,r2…..rn]-f->[Ra,Rb,Rc,Rd]
3. fsum:: ((_,_)-+->,(_,_)-+->)-+->()

layer

1. layer define a set of parallel transactions
2. {f1,f2,f3} all transaction in the layer executed in parallel, if there are common node between function’s in/out put, it will be pipelined.

grammar

1.