低功耗设计优化十点

Ptotal = Csw . Freq. Vdd.Vdd + Pleakage + Pshort + Pglitch 总功耗 = 网路电容 x 频率 x 电源电压^2 + 漏电流功耗 + 短路功耗 + 毛刺功耗

Optimize the architecture for low power 低功耗架构优化 Reduce the voltage 降低电压 Reduce the switching activity 减少切换活动 Reduce the glitches 减少毛刺（逻辑消噪） Control the rise and fall time of the important signals Reduce the number of global signals 减少全局信号（low fanout 低扩散， distributive，non-centralise 分布式） Optimize the cells/circuits for low power 优化电路单元（精简，稳定，少冗余） Reduce rhe cross talk 减少串扰 Bias the substrate 偏置基底 Plan, estimate and optimize for power in every stage 计划，评估，优化每一阶段

1. Optimize the architecture for low power Earlier you optimize your design for power it is better and more effective. You can optimize the architecture in many ways. You can optimize the type, size, frequency and bus width of memory. Consider routing resources to be used and effect of loading while deciding bus grouping. As the wire delays play a major role in deep submicron era, minimize the global signals. Consider operating device in low power modes whenever feasible. 2. Reduce the voltage As shown in the expression impact of Voltage on power is quadratic. It reduces the speed of the design too. Decide which voltage gives optimum speed. There can be multiple voltage rails for different parts of the design. Take care the timing at the interface of multiple voltages. This is a very effective method to control power and widely used. 3. Reduce the switching activity Since all blocks of the design needn't be active all the time, we can reduce the average power of the chip by gating the clock for the inactive parts. This method is very effective when the chip has multiple blocks and only few will be active at a time or when off time of the chip is significant. This is a traditional method used in earlier technologies too. Simplicity is at its best here. Partitioning the logic to suit this style can make this very effective. 4. Reduce the glitches Unwanted transitions play a major role in power consumption. This is mainly so, if the combinatorial logic is too deep. You can minimize this by prioritizing the signals such that transitions can be minimized. Proper design practices or ground rules can be helpful. Some time, even slow gates can make the difference. 5. Control the rise and fall time of the important signals Some signals in the design may be not critical for the timing. Still make sure they are not overloaded, such that transition time can trouble. 6. Reduce the number of global signals Global signals are always a problem. They need to be addressed for the timing. Since the wire capacitance plays a major role when technology shrinks the minimum size to 90nm and beyond. Optimize inter block communication for low power. 7. Optimize the cells/circuits for low power This is one of the time tested technique to reduce power. Logic based on pass transistors can be of great help if the design needs repeated data path structures like adders and multipliers. You can optimize the cells for low power and place with minimum wire loading. This can be very effective for structured data path style applications. 8. Reduce the cross talk New technologies make this a necessity. As the metal walls grow taller and shrink the gap with neighbors, this problem becomes dominant. There are many methods to reduce this and everything need to be analyzed and practiced if you are in 90nm and beyond. 9. Bias the substrate This is one more area brought to front by deep sub micron era, as leakage power is no more negligible. You can use this to reduce the power when the chip is not operating. 10. Plan, estimate and optimize for power in every stage Most important rule for low power design is to plan, estimate and optimize the design for power in the every possible stage. At some stage, estimation can be easy using design automation tools. In some other stages, you have to rely on approximates and assumptions.