asynchronous circuit problem

First of all synchronous designs are more reliable. They are deterministic in their behavior due to the fact that all signals are sampled at a well-defined time interval. Synchronous designs rely on very few timing parameters to guarantee operation namely the maximum frequency of operation of a device (fmax) the register setup and hold times (tSU and tH) and the register clock-to-output time (tCO). Meeting these parameters ensures designs will work under temperature voltage and process variations.
Synchronous designs are also portable. In all PLDs and ASICs the master clock or clocks are routed via a low-skew clock network. These networks ensure that a design done in one PLD architecture will be compatible with a different architecture with good results. Synchronous designs take advantage of this trait.
In addition synchronous designs can be tested more easily and run statically with the clock input driven by a test signal. They can be made virtually immune to noise. Therefore finding errors in a design will not be a cross between identifying logic errors and tracking down noise-induced errors.
Synchronous designs attain performance levels easily. The maximum operational frequency of a synchronous design can be determined from the data sheet for many PLDs. Determining maximum performance of circuitsthat include asynchronous clocking events is much more complicated.
Finally synchronous designs are easier to code in a hardware description language (HDL) and are also easier to read. Designs built around a common clock yield compact efficient code. On the other hand designs with numerous clocks and asynchronous behavior are more difficult to understand. Their code descriptions can also get cumbersome.

To avoid race effects and deadlock effect synchronous circuits are used

Synchronous circuit is sample based

1. it also can have handshake –> asynchronous behaviour

Asynchronous circuit is filter based

1. it use control(ack/req) signal to help decode the information from the data channel.
2. since control signal is in a loop, it may not be deterministic
3. extra noise and interconnect may cost more power when the circuit network become large

IEEE Computer Society System Competition

http://www.computer.org/portal/web/competition/home

 

ISA

NFDL(network flow description language)

Flow

1. data ()
2. control
3. instructions
4. state (FSMs)

node, link, layer

nodes

1. 32 regs
2. r(i) or r(i:j) or ra(rb) to access bit/bits
3. reg vectors
   1. [r1,r2,r3].(0:1)
   2. vector also support sub accessing

Link

1. single transaction as a function of input nodes and output nodes
2. [r1,r2…..rn]-f->[Ra,Rb,Rc,Rd]
3. fsum:: ((_,_)-+->,(_,_)-+->)-+->()

layer

1. layer define a set of parallel transactions
2. {f1,f2,f3} all transaction in the layer executed in parallel, if there are common node between function’s in/out put, it will be pipelined.

grammar

1.   

Social network 2.0

Play

human computation

ESP game http://www.gwap.com/gwap/

utilise human curiosity (who, why, reward, soul mate)

Learn

Language partner, problem solving

towards collaborative achievement    

Connect

class of people as actor

inter class relationship (parent class, child class, peer class)

information flow in the class network.

layering for subnet of class network

 

Submission

http://www.ieeechangetheworld.org/submission/register.html

Problem Description

 

Impact on Humanity

if this network become real,

* Project Title:
(max 25 words)

Social Network 2.0

Problem Description (Optional):
(max 250 words)
Describe the problem you're trying to solve and what about the project intrigued you in the first place.

Social Interaction has always been an essential way for people to learn knowledge and solve problems, but how far have we harnessed it potential other than just using emails, Facebook and Twitterr. we definitely need a new platform for people to learn, communicated and interact.

Impact on Humanity:
(max 250 words)
Describe how your project benefits your community and/or humanity. Provide specific examples.

With today’s information technology, our ability to learn and communicate has significantly changed our life, and it’s still evolving every few years. But how much power have we really unleashed? how often do we spend long time to search on internet, play games, checking social networking site, etc. Is there a way to blend all of them together? connecting like minded people who can help each other, setting some game rules as a Turing complete problem solver, or even learn new languages from each other.  

Solution:
(max 2,500 words)
Describe in detail how you have solved the problem described above using engineering, science, computing and leadership skills. Include specifics on your approach, such as any research or planning conducted prior to execution, as well as detailed explanations of tactics employed to achieve the desired result. You can upload an appendix document to further support your solution.

Play

we all play games everyday, as long as there is set of rules and competition, we are in the game. Evolution is such a classic example, and the result is we are actually solving problems of life quality through this process of playing a game.

people have actually came out with the idea of human computation (eg ESP Game ), and what it does is exactly using game to solve problems such as image labelling, and the result is very interesting, but the problem is people feel gaining little reward when playing the game. and some times no rewards at all when playing with a robot.

Learn

we all want to get maximum rewards when playing a game, and the best reward is often solving a problem. if we can create a set of rules where people can help each other solving problems, learning new languages, achieve some thing collaboratively. we not only can improving the gaming experience, but also help people in real life.

Connect

Like people attract, when we have played with someone, we can tell whether someone is like minded or not, and then they can be connected in a class system, one they are in the class network, information flow in the network will be much more efficient, people can broadcasting text or video based information to specific networks, and people can also set rules to only receive information from specific networks. sounds like twitter ? but it more powerful.

Building a Electronic lab in VMware

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Android Dev on Ubuntu 9.10

Per-install

1. Java 1.5.0 in Ubuntu 9.10
   1. go to http://java.sun.com/javase/downloads/index_jdk5.jsp download  JDK 5 update 22, this product is no longer officially supported, so need to submit a form and download from the link they send it to your email.
   2. the file downloaded will be xxxx.rpm.bin
   3. get rpm if you don’t have it, sudo apt-get install rpm
   4. then run the bin file (./)
   5. rmp –i xxxxx.rpm  --orce-debian –nodeps
   6. sudo update-alternatives --install /usr/bin/java java/usr/java/jdk1.5.0_22/bin/java 50
   7. sudo update-alternatives --install /usr/bin/javac javac/usr/java/jdk1.5.0_22/bin/javac 50
   8. sudo apt-get install git-core gnupg flex bison gperf build-essential zipcurl zlib1g-dev gcc-multilib g++-multilib libc6-dev-i386 lib32ncurses5-dev ia32-libs x11proto-core-dev libx11-dev lib32readline5-dev lib32z-dev
2. other part follow http://source.android.com/download
   1. remember to add PATH=$PATH:$HOME/bin before run repo command
   2. export  PATH=$PATH:$HOME/bin
   3. export JAVA_HOME/bin:$PATH

post install

1. eclipse IDE http://source.android.com/using-eclipse

月夜

明月几时有，

云烟飘人间。

举头望明月，

低头生死间。

低功耗设计优化十点

Ptotal = Csw . Freq. Vdd.Vdd + Pleakage + Pshort + Pglitch 总功耗 = 网路电容 x 频率 x 电源电压^2 + 漏电流功耗 + 短路功耗 + 毛刺功耗

Optimize the architecture for low power 低功耗架构优化 Reduce the voltage 降低电压 Reduce the switching activity 减少切换活动 Reduce the glitches 减少毛刺（逻辑消噪） Control the rise and fall time of the important signals Reduce the number of global signals 减少全局信号（low fanout 低扩散， distributive，non-centralise 分布式） Optimize the cells/circuits for low power 优化电路单元（精简，稳定，少冗余） Reduce rhe cross talk 减少串扰 Bias the substrate 偏置基底 Plan, estimate and optimize for power in every stage 计划，评估，优化每一阶段

1. Optimize the architecture for low power Earlier you optimize your design for power it is better and more effective. You can optimize the architecture in many ways. You can optimize the type, size, frequency and bus width of memory. Consider routing resources to be used and effect of loading while deciding bus grouping. As the wire delays play a major role in deep submicron era, minimize the global signals. Consider operating device in low power modes whenever feasible. 2. Reduce the voltage As shown in the expression impact of Voltage on power is quadratic. It reduces the speed of the design too. Decide which voltage gives optimum speed. There can be multiple voltage rails for different parts of the design. Take care the timing at the interface of multiple voltages. This is a very effective method to control power and widely used. 3. Reduce the switching activity Since all blocks of the design needn't be active all the time, we can reduce the average power of the chip by gating the clock for the inactive parts. This method is very effective when the chip has multiple blocks and only few will be active at a time or when off time of the chip is significant. This is a traditional method used in earlier technologies too. Simplicity is at its best here. Partitioning the logic to suit this style can make this very effective. 4. Reduce the glitches Unwanted transitions play a major role in power consumption. This is mainly so, if the combinatorial logic is too deep. You can minimize this by prioritizing the signals such that transitions can be minimized. Proper design practices or ground rules can be helpful. Some time, even slow gates can make the difference. 5. Control the rise and fall time of the important signals Some signals in the design may be not critical for the timing. Still make sure they are not overloaded, such that transition time can trouble. 6. Reduce the number of global signals Global signals are always a problem. They need to be addressed for the timing. Since the wire capacitance plays a major role when technology shrinks the minimum size to 90nm and beyond. Optimize inter block communication for low power. 7. Optimize the cells/circuits for low power This is one of the time tested technique to reduce power. Logic based on pass transistors can be of great help if the design needs repeated data path structures like adders and multipliers. You can optimize the cells for low power and place with minimum wire loading. This can be very effective for structured data path style applications. 8. Reduce the cross talk New technologies make this a necessity. As the metal walls grow taller and shrink the gap with neighbors, this problem becomes dominant. There are many methods to reduce this and everything need to be analyzed and practiced if you are in 90nm and beyond. 9. Bias the substrate This is one more area brought to front by deep sub micron era, as leakage power is no more negligible. You can use this to reduce the power when the chip is not operating. 10. Plan, estimate and optimize for power in every stage Most important rule for low power design is to plan, estimate and optimize the design for power in the every possible stage. At some stage, estimation can be easy using design automation tools. In some other stages, you have to rely on approximates and assumptions.

Apple 多点触摸的秘密

从patendocs找到了apple的multi touch专利档案，

http://www.faqs.org/patents/app/20080309631

内容很长，因为经过一些分析，ctrl+F 找multiplex，结果如下

[0024]A single touch sensing panel (i.e., a pane; capable of sensing a single touch event at a time only) can be similar to panel 100. In some embodiments, a single touch sensing panel can feature simpler touch sensing circuitry. For example, it may feature a single sensing circuit 103 which is time multiplexed to the different data lines 102. In other words, the various data lines can be periodically connected to the single sensing circuit.

[0035]In a single touch sensing panel, stimulus lines can be deactivated in the manner discussed above. If multiple sensing circuits are used (e.g., one per data line), data lines can also be deactivated in the manner discussed above. If a single time multiplexed sensing circuit is used, specific data lines can be deactivated by not connecting these data lines to the single sensing circuit.

结论就是，电容屏幕是不可能有独立信道的同时多点采样的。所以5点以上的采样将会是一个响应较慢的系统，游戏性能将会降低，除非在屏幕上空分独立区域，这样或许还可以。

道德與自由，追憶八九六四

一 切真理都是宣传，一切历史也是如此，我们的所听，所闻，也许永远都不是绝对的客观，但是也许只有从多样的主观意见中，我们才能找到一个能与自我意识共鸣的 理解。冲突和死亡，可以说是每一个悲剧的关键词，但是斗争和胜利，又可以是同一件事的反面写照。我想，面对历史，通常最有价值的不是发生了什么，而是它为 什么会发生。因为只有当我们知道了为什么，我们才能够以史为鉴，面向未来。



20年前，就有这么一个值得我们去思考的事件，虽然历史已经远去，可是其影响却不可谓不深远。

这 件事大环境是一个世界正处于冷战的最后阶段，以人道主义为核心的新思维运动，在社会主义阵营内产生广泛影响。虽然中华人民共和国官方严防“资产阶级自由化 ”的西方民主思潮，但社会已浮现不安情绪。从1988年底至1990年代初，中央委员会全体会议及人大会议会议已提出各种问题，包括通胀、粮食减产、工人 骚动不安、失控的人口流动、贪污、人口高速增长。从世界的角度看，六四运动并非孤立的事件，而是当时各地社会主义国家民主化的一环。六四事件发生当天，波 兰团结工会在大选中获胜，推翻社会主义制度；数月后，东欧社会主义国家也先后发生和平演变，两年后苏联亦宣告解体。

无 论什么年代，如思潮，学运，冲突，这样的大事件，对那些理想和善良的中国人而言，是一个热情驱使的冲动。对投机和算计的中国人而言，则是欲望驱使的躁动。 而对剩下的那些市井之徒，因为无需担当责任，所以也就加入一起浑水摸鱼。其实从某种角度来看，这也和加入共产党的成员颇有相似之处，有的人为了国家，有的 人为了权力，有的就是为了有口饭吃。但是共产党却成功了，虽然赢得并不光彩，但是却反映了一个悲观的现实，中国人喜欢内斗，向往权欲，因为中国人总体的文 化基础和人文素质还很薄弱。



仔 细想来，中华民族近百年来的一切灾难不都是因为中国人对权力的过度渴望吗。从明末的吴三桂，到清末的慈禧，再到袁世凯，蒋介石，毛泽东。中国从一个世界强 国沦落到一个任人宰割，内战纷争的乱世。这近百年间，欧洲，美国的人民在发展中不断地提高了自己国民的素质，而中国却一直止步不前，在中学西学之间，帝国 与宪政之间，民主与专政之间，党派与主义之间，互相纠缠，斗争，却忘记了解决问题的关键不是党，主义，政治。而是决定未来的教育。有了教育，人们才会慢慢 意识到什么才是在法律和道德维持下的公平竞争，在获取和付出平衡下的持续发展，在个人和国家之间的道德取舍，在武力维持和平下的文化战争。才会知到自己拥 有民主和自由的同时肩负着更重的责任，我想那时人们才更会关注我们需要的主义是什么，而中国人千年来的主义又是什么。

没有强大的中国和高素质的人民，什么民主都是表面文章，我承认我恨独裁，但我同时也承认民主不能解决一切问题，腐败问题根源是在人的贪婪，人是需要教育 的，但这个绝不是一两天的事情。六四事件虽然已经过去20年了，但是有多少人还在思考发生了什么，又有多少人在思考为什么它会发生呢？每个人都在为自己信 仰的价值观做宣传。但是，权力越大，责任越大。希望全世界的中国人，努力学习，以实力证明自己，我们可以肩负这个决定民族命运的责任。

FPGA综合工具Synplify 9.61下载与破解

Synplicity Synplify Premier v9.6.1 with Identify v3 下载地址

megaupload

Part 1 http://www.megaupload.com/?d=Z26EN7ZK Part 2 http://www.megaupload.com/?d=DNG7GWFX Part 3 http://www.megaupload.com/?d=27QKSQGK Part 4 http://www.megaupload.com/?d=64U8N2I3

--=oo0oo=--

rapidshare

Part 1 http://rapidshare.com/files/154151325/Synplicity.Synplify.Premier.v9.6.1.with.Identify.v3.0-Lz0.part1.rar Part 2 http://rapidshare.com/files/154151413/Synplicity.Synplify.Premier.v9.6.1.with.Identify.v3.0-Lz0.part2.rar Part 3 ttp://rapidshare.com/files/154151374/Synplicity.Synplify.Premier.v9.6.1.with.Identify.v3.0-Lz0.part3.rar Part 4 http://rapidshare.com/files/154151271/Synplicity.Synplify.Premier.v9.6.1.with.Identify.v3.0-Lz0.part4.rar

--=oo0oo=--


uploaded.to

Part 1 http://uploaded.to/?id=h4osh6 Part 2 http://uploaded.to/?id=ylrowk Part 3 http://uploaded.to/?id=x2nx65 Part 4 http://uploaded.to/?id=b47914

--=oo0oo=--

破解方法：

1） 把文件ibfs32.dll复制到系统windows\system32

2） 随便把文件synplctyd.lic复制到什么地方

3） 打开synplctyd.lic文件, 把文件中所有HOSTID=000C29FC37B9这个=号后数值替换为你电脑的MAC地址，再保存。

查计算机MAC地址方法

在Windows 2000/XP的计算机系统中

依次单击“开始”→“运行”→输入“cmd”→回车,在出现的命令提示符界面中输“ipconfig /all”→回车，可以得到计算机的MAC地址

4. 设置环境变量的SYNPLCTYD_LICENSE_FILE的变量值为synplctyd.lic文件所存放的地址 (e.g. c:\windows\synplctyd.lic)

我的电脑—右键—属性—高级—环境变量—用户变量—SYNPLCTYD_LICENSE_FILE——编辑

好了，安装完毕，可以使用了。