asynchronous circuit problem

First of all synchronous designs are more reliable. They are deterministic in their behavior due to the fact that all signals are sampled at a well-defined time interval. Synchronous designs rely on very few timing parameters to guarantee operation namely the maximum frequency of operation of a device (fmax) the register setup and hold times (tSU and tH) and the register clock-to-output time (tCO). Meeting these parameters ensures designs will work under temperature voltage and process variations.
Synchronous designs are also portable. In all PLDs and ASICs the master clock or clocks are routed via a low-skew clock network. These networks ensure that a design done in one PLD architecture will be compatible with a different architecture with good results. Synchronous designs take advantage of this trait.
In addition synchronous designs can be tested more easily and run statically with the clock input driven by a test signal. They can be made virtually immune to noise. Therefore finding errors in a design will not be a cross between identifying logic errors and tracking down noise-induced errors.
Synchronous designs attain performance levels easily. The maximum operational frequency of a synchronous design can be determined from the data sheet for many PLDs. Determining maximum performance of circuitsthat include asynchronous clocking events is much more complicated.
Finally synchronous designs are easier to code in a hardware description language (HDL) and are also easier to read. Designs built around a common clock yield compact efficient code. On the other hand designs with numerous clocks and asynchronous behavior are more difficult to understand. Their code descriptions can also get cumbersome.

To avoid race effects and deadlock effect synchronous circuits are used

Synchronous circuit is sample based

1. it also can have handshake –> asynchronous behaviour

Asynchronous circuit is filter based

1. it use control(ack/req) signal to help decode the information from the data channel.
2. since control signal is in a loop, it may not be deterministic
3. extra noise and interconnect may cost more power when the circuit network become large