DSP has turned out to be one of the most important technologies in the development of communications systems and other electronics. After Marconi and Armstrong’s invention of basic radio communication and transceivers, users were soon unsatisfied with the poor communication quality. The noise was high and the bandwidth utility was inefficient. Parameters changed due to variations in temperature, and the signals could not be reproduced exactly. In order to improve the quality, analogue radio communication had to give way to digital radio communication.
Coding for communications can be further divided into reliable coding (for error detection and error correction) and efficient coding (compression).
Without special hardware acceleration,the performance of Huffman coding and decoding is usually much lower than one bit per instruction. With special hardware acceleration, two bits per instruction can be achieved. Huffman coding and decoding are typical applications for a FSM (Finite State Machine).
Voice (speech) compression has been thoroughly investigated, and advanced voice compression today is based on voice synthesis techniques.
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it’s quite a good book in DSP processor design, and here is some of my thoughts.
Most current DPS algorithms are predictable, streaming computing is currently sufficient. However, more intelligent DSP applications are emerging and introduced such as language recognition, etc. Searching and sorting algorithms are used by intelligent signal processing. We therefore plan to analyze behaviours of most used sequential algorithms in intelligent DSP and implement them into ASIP.
Systolic array
- MIMD like engine
- reduce Load/Store instructions by evolving data on the array
- controlled by MIMD like instructions with loop-able syntax
Analogue computation
when accuracy and computation result need not to be point but range reproducible. it is a good candidate for power,performance and area improvements.
- pros
fast, low power, smaller size, addition is almost free, just merge wires
- cons
noisy, not good for multiplication or differentiation, need extra ADC, DAC interface.
read more at
http://hrl.harvard.edu/analog/
some time adding electrons together is much elegant than using them as fuels for the ALUs… but only some times!
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some old thoughts about systolic array, FYC, I merge it into DSP area.
systolic array was a hot research topic in the 80’s, but just like all the other parallel computing research, they all suppressed by the exponential performance growth of sequential machine offered by Moore's law.
but things will not always go faster, the sequential machines has certainly reached a wall in terms of both power and speed.
so it make us start rethinking parallel, and especially how software behaves and hardware implementation to match them.
the are few concepts are very helpful.
- computer architecture design is a optimization process which find best solution to match the software-hardware behaviour given the constrains of communication and computation cost.
- as the transistor size shrinks, clock frequency increases, the communication cost is getting bigger than computation.
- many techniques such as cache, parallel memory banks, data pre-allocation, traffic data compression, or even dynamic traffic optimization. were used to balance the imbalance of communication and computation.
- if software = algorithm + data structure, then they both adaptable to hardware environment. but if the adaptation has reduced the performance of the software too much, hardware will also adapts to software to better match it’s behaviour. such as GPUs and OpenGL.
- model based design is very useful to capture software behaviours.
- systolic and cellular array provided MIMD like behaviour with looping capabilities.
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