quantum entanglement and six degree of connection

if you feel stressed, it actually means your another live is calling you, is that amazing?

we all lived in two lives in the time span of our existence. in fact, 1/3 is the normal world, 1/3 in dream world and 1/3 doing nothing.

a interesting fact is, the dream world is non-causal and the normal world is causal. a duality just like the wave-partial duality in physics.

when you try to observe which live you are living, the duality disappear. and that’s what we are mostly thinking about the normal world and it’s duality pair.

so, once we accept the two lives theory, we can now make further conclusions about the “real world”.

fact 1, we are all connected, and our live depend on it, when things connected, they have share a common live, a duality live if you will. such things are (electron cloud, C60, VLSI circuit, neuron network (== our brain), society etc…  )

fact 2, the “secret” is right, what you think determines reality, and the secret of the “secret” is what to think. it up to your perspective, still thinking in the normal world? try to see it as a duality.

fact 3, entanglement of quantum physics is limited by distance, because the connect is limited in space, but what about  entanglement in our society? although we don’t know  everyone in the society, but we all connected, that’s why six degree of connection come to our mind. you may ask what if someone who has no connection at all, then he/she is not living from our perspective of “living”.

asynchronous circuit problem

First of all synchronous designs are more reliable. They are deterministic in their behavior due to the fact that all signals are sampled at a well-defined time interval. Synchronous designs rely on very few timing parameters to guarantee operation namely the maximum frequency of operation of a device (fmax) the register setup and hold times (tSU and tH) and the register clock-to-output time (tCO). Meeting these parameters ensures designs will work under temperature voltage and process variations.
Synchronous designs are also portable. In all PLDs and ASICs the master clock or clocks are routed via a low-skew clock network. These networks ensure that a design done in one PLD architecture will be compatible with a different architecture with good results. Synchronous designs take advantage of this trait.
In addition synchronous designs can be tested more easily and run statically with the clock input driven by a test signal. They can be made virtually immune to noise. Therefore finding errors in a design will not be a cross between identifying logic errors and tracking down noise-induced errors.
Synchronous designs attain performance levels easily. The maximum operational frequency of a synchronous design can be determined from the data sheet for many PLDs. Determining maximum performance of circuitsthat include asynchronous clocking events is much more complicated.
Finally synchronous designs are easier to code in a hardware description language (HDL) and are also easier to read. Designs built around a common clock yield compact efficient code. On the other hand designs with numerous clocks and asynchronous behavior are more difficult to understand. Their code descriptions can also get cumbersome.

To avoid race effects and deadlock effect synchronous circuits are used

Synchronous circuit is sample based

1. it also can have handshake –> asynchronous behaviour

Asynchronous circuit is filter based

1. it use control(ack/req) signal to help decode the information from the data channel.
2. since control signal is in a loop, it may not be deterministic
3. extra noise and interconnect may cost more power when the circuit network become large

IEEE Computer Society System Competition

http://www.computer.org/portal/web/competition/home

 

ISA

NFDL(network flow description language)

Flow

1. data ()
2. control
3. instructions
4. state (FSMs)

node, link, layer

nodes

1. 32 regs
2. r(i) or r(i:j) or ra(rb) to access bit/bits
3. reg vectors
   1. [r1,r2,r3].(0:1)
   2. vector also support sub accessing

Link

1. single transaction as a function of input nodes and output nodes
2. [r1,r2…..rn]-f->[Ra,Rb,Rc,Rd]
3. fsum:: ((_,_)-+->,(_,_)-+->)-+->()

layer

1. layer define a set of parallel transactions
2. {f1,f2,f3} all transaction in the layer executed in parallel, if there are common node between function’s in/out put, it will be pipelined.

grammar

1.